The invention relates to an apparatus and a method for spectrally shaping a reference clock signal for a converter, particularly for a digital-analogue converter, which is provided in the feedback loop of a sigma-delta modulator.
Clock signal jitters are a source of error in converters, particularly in clocked digital-analogue converters. Digital-analogue converters may, inter alia, also be used in feedback loops in sigma-delta analogue-digital converters.
FIG. 1 shows a block diagram of a sigma-delta analogue-digital converter based on the prior art. The analogue-digital converter ADC converts an analogue input signal into digital data or into a digital data stream. These data are then processed further and stored. The analogue-digital converter quantizes the continuous analogue input signal both in terms of time and in terms of amplitude. The digital output signal is stepped following the conversion. In the case of a sigma-delta analogue-digital converter, as shown in FIG. 1, the analogue input signal X(t) is supplied to a subtractor, which subtracts an analogue feedback signal produced by a digital-analogue converter DAC. The difference signal is integrated by an integrator and is then compared with a threshold value by a comparator. The digital output signal from the comparator is fed back to the digital-analogue converter DAC, which converts a digital output value to produce an analogue voltage which is subtracted from the input signal by means of the subtractor. A digital filter connected downstream of the sigma-delta analogue-digital converter converts the serial and high-frequency bit stream into digital values which reproduce the analogue value at the input of the sigma-delta analogue-digital converter at a lower rate but at a very high resolution. The comparator and the digital-analogue converter DAC are clocked by a reference clock signal. The digital-analogue converter used in the feedback path is conventionally a current-controlled digital-analogue converter.
A drawback of sigma-delta analogue-digital converters based on the prior art is that they are particularly sensitive towards clock signal jitters. If the reference clock signal which clocks the digital-analogue converter DAC fluctuates over time, this clock signal jitter results in noise being injected into the feedback signal. The noise caused by the clock signal jitter is brought about by the slight changes in energy or changes in the area of the pulses generated by the current-controlled digital-analogue converter DAC. By contrast, digital-analogue converters using switched-capacitor technology are based on transfer of charges Q between the capacitors, the charge being almost independent of small variations in the clock signal. However, digital-analogue converters which are produced using switched-capacitor technology have the drawback that they are relatively slow, since the charge reversal operations take a relatively long time. Although current-controlled digital-analogue converters which produce current pulses whose amplitude is proportional to a digital value operate relatively quickly, they are sensitive towards clock signal jitters.
FIG. 2 shows a general block diagram of a conventional digital-analogue converter DAC which is clocked by a reference clock signal CLKref. The digital-analogue converter DAC receives a digital input signal from a data source, which is likewise clocked by the reference clock signal, and converts it into an analogue output signal. The output signal from the digital-analogue converter DAC is a sequence of square-wave pulses which are weighted with the digital input value and which have a predetermined time period Ts. If the reference clock signal has a clock signal jitter, the duration of the clock pulses deviates from the ideal instant Ts, as shown in FIG. 3. The instants at which the output signal from the current-controlled digital-analogue converter DAC changes can be defined as follows:τ=nTs+β[n]where β[n] is the periodically occurring jitter. The periodically occurring jitter forms a random noise signal with a constant variance which is generated when the reference clock signal CLKref is produced, for example by a PLL (Phase Locked Loop) circuit. The error signal obtained between the ideal output signal from the digital-analogue converter DAC and the actual output signal is as follows:
      e    ⁡          (      t      )        =                              y          idcal                ⁡                  (          t          )                    -              y        rcal            -              (        t        )              =                  ∑                  k          =          0                ∞            ⁢                        (                                    u              ⁡                              (                                  t                  -                                      (                                                                  β                        ⁡                                                  [                          k                          ]                                                                    +                                              kT                        S                                                              )                                                  )                                      -                          u              ⁡                              (                                  t                  -                                      kT                    S                                                  )                                              )                ·                  (                                    y              ⁡                              [                k                ]                                      -                          y              ⁡                              [                                  k                  -                  1                                ]                                              )                    The error signal is shown in FIG. 3B. The area obtained for an error pulse within a sampling interval is as follows:s[n]=β[n]·(y[n]−y[n−1])If the integral of the error signal is calculated as the sum of the error signal pulse areas and this is sampled for the instants T=n·Ts then the following integrated error signal q[n] is obtained:
            q      ⁡              (        t        )              =                  ∫        o        t            ⁢                        e          ⁡                      (            τ            )                          ·                  ⅆ          τ                                q      ⁡              [        n        ]              =                  q        ⁡                  (                      nT            S                    )                    =                        ∑                      k            =            0                    n                ⁢                              β            ⁡                          [              k              ]                                ·                      (                                          y                ⁡                                  [                  k                  ]                                            -                              y                ⁡                                  [                                      k                    -                    1                                    ]                                                      )                              The integrated error signal sequence q[n] can be expressed as follows:q[n]=s[n]+q[n−1]Z transformation produces the following:S(z)=(1−z−1)·O(z)
The error signal shown in FIG. 3B is the error caused by the clock signal jitter.